1. Field of the Invention
The present invention relates to a semiconductor non-volatile memory having a floating gate, and more particularly to a semiconductor non-volatile memory in which a floating gate is provided above a control gate.
2. Description of the Related Art
A non-volatile memory, in which a control gate is provided on an insulating film grown on a floating gate, has a problem in that the insulating film grown on the polycrystalline silicon floating gate has a large leakage current and a small withstand voltage. As a floating gate non-volatile memory for solving the problem, there is disclosed a structure in which: a floating gate is provided on a channel forming semiconductor region sandwiched by a source region and a drain region through an insulating film; the floating gate is extended onto an insulating film grown on a single crystal control region; and the single crystal control region is used as a control gate (refer to JP 57-49148 B, FIG. 3).
On the other hand, there has been separately developed a technique in which an insulating film with a small leakage current and an excellent withstand voltage is formed on a polycrystalline silicon floating gate; however, the technique shares few manufacturing processes with that of a MOS logic. Therefore, the floating gate non-volatile memory having the single crystal control region has been utilized as a non-volatile memory appropriate for being embedded in a MOS logic shortly after JP57-49148B was disclosed. In this case, the single crystal control region is formed in a surface of a semiconductor substrate as a semiconductor region of an opposite conductivity type to a substrate.
In these days, the lowering of a power supply voltage of IC/LSI has progressed, which makes a potential control in a small voltage range of a floating gate important. Thus, the following problem has arisen.
That is, (1) an electric potential of an interconnection, which is arranged above the floating gate (in the state of not contacting with and being separated from the floating gate), has a capacitive coupling with the floating gate. As a result, a gate threshold voltage of a floating gate non-volatile memory measured from a single crystal control region varies.
(2) When even one part in and on an insulating film on the floating gate is included or attached with electric charge, the gate threshold voltage of the floating gate non-volatile memory measured from the single crystal control region varies.
The electric charge included into the insulating film is generated when discharge of a source gas is excited immediately above a wafer in plasma CVD or the like, to deposit the insulating film on the floating gate. The electric charge on the insulating film is generated due to contamination of a surface of the wafer or chip, or discharge from a handling jig.
The effect of the interconnection arrangement is not considered in many cases at the time of design of the floating gate non-volatile memory, and an amount of the included or attached electric charge cannot be predicted. Therefore, the gate threshold voltage of the completed floating gate non-volatile memory measured from the single crystal control region is difficult to predict.